laser_stabilisation/microcontroller/ADuC702x.lst

ARM Macro Assembler    Page 1 


    1 00000000         ;/******************************************************
                       ***********************/
    2 00000000         ;/* STARTUP.S: Startup file for ADI ADuC702x device seri
                       es                    */
    3 00000000         ;/******************************************************
                       ***********************/
    4 00000000         ;/* <<< Use Configuration Wizard in Context Menu >>>    
                                             */ 
    5 00000000         ;/******************************************************
                       ***********************/
    6 00000000         ;/* This file is part of the uVision/ARM development too
                       ls.                   */
    7 00000000         ;/* Copyright (c) 2005-2006 Keil Software. All rights re
                       served.               */
    8 00000000         ;/* This software may only be used under the terms of a 
                       valid, current,       */
    9 00000000         ;/* end user licence from KEIL for a compatible version 
                       of KEIL software      */
   10 00000000         ;/* development tools. Nothing else gives you the right 
                       to use this software. */
   11 00000000         ;/******************************************************
                       ***********************/
   12 00000000         
   13 00000000         
   14 00000000         ;/*
   15 00000000         ; *  The STARTUP.S code is executed after CPU Reset. Thi
                       s file may be 
   16 00000000         ; *  translated with the following SET symbols. In uVisi
                       on these SET 
   17 00000000         ; *  symbols are entered under Options - ASM - Define.
   18 00000000         ; *
   19 00000000         ; *  RAM_INTVEC: when set the startup code copies except
                       ion vectors 
   20 00000000         ; *  from on-chip Flash to on-chip RAM and remaps RAM to
                        address 0.
   21 00000000         ; */
   22 00000000         
   23 00000000         
   24 00000000         ; Standard definitions of Mode bits and Interrupt (I & F
                       ) flags in PSRs
   25 00000000         
   26 00000000 00000010 
                       Mode_USR
                               EQU              0x10
   27 00000000 00000011 
                       Mode_FIQ
                               EQU              0x11
   28 00000000 00000012 
                       Mode_IRQ
                               EQU              0x12
   29 00000000 00000013 
                       Mode_SVC
                               EQU              0x13
   30 00000000 00000017 
                       Mode_ABT
                               EQU              0x17
   31 00000000 0000001B 
                       Mode_UND
                               EQU              0x1B



ARM Macro Assembler    Page 2 


   32 00000000 0000001F 
                       Mode_SYS
                               EQU              0x1F
   33 00000000         
   34 00000000 00000080 
                       I_Bit   EQU              0x80        ; when I bit is set
                                                            , IRQ is disabled
   35 00000000 00000040 
                       F_Bit   EQU              0x40        ; when F bit is set
                                                            , FIQ is disabled
   36 00000000         
   37 00000000         
   38 00000000         ;// <h> Stack Configuration (Stack Sizes in Bytes)
   39 00000000         ;//   <o0> Undefined Mode      <0x0-0xFFFFFFFF:8>
   40 00000000         ;//   <o1> Supervisor Mode     <0x0-0xFFFFFFFF:8>
   41 00000000         ;//   <o2> Abort Mode          <0x0-0xFFFFFFFF:8>
   42 00000000         ;//   <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
   43 00000000         ;//   <o4> Interrupt Mode      <0x0-0xFFFFFFFF:8>
   44 00000000         ;//   <o5> User/System Mode    <0x0-0xFFFFFFFF:8>
   45 00000000         ;// </h>
   46 00000000         
   47 00000000 00000080 
                       UND_Stack_Size
                               EQU              0x00000080
   48 00000000 00000080 
                       SVC_Stack_Size
                               EQU              0x00000080
   49 00000000 00000080 
                       ABT_Stack_Size
                               EQU              0x00000080
   50 00000000 00000080 
                       FIQ_Stack_Size
                               EQU              0x00000080
   51 00000000 00000080 
                       IRQ_Stack_Size
                               EQU              0x00000080
   52 00000000 00000400 
                       USR_Stack_Size
                               EQU              0x00000400
   53 00000000         
   55 00000000 00000680 
                       Stack_Size
                               EQU              (UND_Stack_Size + SVC_Stack_Siz
e + ABT_Stack_Size +                           FIQ_Stack_Size + IRQ_Stack_Size
 + USR_Stack_Size)
   56 00000000         
   57 00000000                 AREA             STACK, NOINIT, READWRITE, ALIGN
=3
   58 00000000         Stack_Mem
                               SPACE            Stack_Size
   59 00000680         
   60 00000680 00000680 
                       Stack_Top
                               EQU              Stack_Mem + Stack_Size
   61 00000680         
   62 00000680         
   63 00000680         ;// <h> Heap Configuration
   64 00000680         ;//   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF>
   65 00000680         ;// </h>



ARM Macro Assembler    Page 3 


   66 00000680         
   67 00000680 00000000 
                       Heap_Size
                               EQU              0x00000000
   68 00000680         
   69 00000680                 AREA             HEAP, NOINIT, READWRITE, ALIGN=
3
   70 00000000         Heap_Mem
                               SPACE            Heap_Size
   71 00000000         
   72 00000000         
   73 00000000         ; MMR definitions
   74 00000000 FFFF0000 
                       MMR_BASE
                               EQU              0xFFFF0000  ; MMR Base Address
   75 00000000 00000220 
                       REMAP_OFFSET
                               EQU              0x0220
   76 00000000 00000404 
                       POWKEY1_OFFSET
                               EQU              0x0404
   77 00000000 00000408 
                       POWCON_OFFSET
                               EQU              0x0408
   78 00000000 0000040C 
                       POWKEY2_OFFSET
                               EQU              0x040C
   79 00000000         
   80 00000000         ;// <e> PLL Setup
   81 00000000         ;//   <o1.0..2>  CD: PLL Multiplier Selection
   82 00000000         ;//               <0-7>
   83 00000000         ;//               <i> CD Value
   84 00000000         ;//   <o1.3>     FINT: Fast Interrupt
   85 00000000         ;//               <0-1>
   86 00000000         ;//               <i> Switches to CD0 for FIQ
   87 00000000         ;// </e>
   88 00000000 00000001 
                       PLL_SETUP
                               EQU              1
   89 00000000 00000001 
                       PLLCFG_Val
                               EQU              0x00000001
   90 00000000         
   91 00000000         
   92 00000000         ;// <e> Pin Setup
   93 00000000 00000000 
                       GPIO_SETUP
                               EQU              0
   94 00000000 FFFFF400 
                       GPIOBASE
                               EQU              0xFFFFF400
   95 00000000         
   96 00000000         ;//   <h>  Port 0
   97 00000000         ;//     <o.0..1>    P0.0  <0=> GPIO      <1=> CMPOUT    
                       <2=> MS2     <3=> PLAI[7]
   98 00000000         ;//     <o.4..5>    P0.1  <0=> GPIO      <1=> ---       
                       <2=> XBEN0   <3=> ---
   99 00000000         ;//     <o.8..9>    P0.2  <0=> GPIO      <1=> ---       
                       <2=> XBEN1   <3=> ---



ARM Macro Assembler    Page 4 


  100 00000000         ;//     <o.12..13>  P0.3  <0=> GPIO      <1=> TRST      
                       <2=> XA16    <3=> ADCBUSY
  101 00000000         ;//     <o.16..17>  P0.4  <0=> GPIO/IRQ0 <1=> CONVSTART 
                       <2=> MS1     <3=> PLAO[1]
  102 00000000         ;//     <o.20..21>  P0.5  <0=> GPIO/IRQ1 <1=> ADCBUSY   
                       <2=> MS0     <3=> PLAO[2]
  103 00000000         ;//     <o.24..25>  P0.6  <0=> GPIO      <1=> MRST      
                       <2=> XAE     <3=> PLAO[3]
  104 00000000         ;//     <o.28..29>  P0.7  <0=> GPIO      <1=> ECLK      
                       <2=> SIN     <3=> PLAO[4]
  105 00000000         ;//   </h>
  106 00000000 00000000 
                       GP0CON_Val
                               EQU              0x00000000
  107 00000000         
  108 00000000         ;//   <h>  Port 1
  109 00000000         ;//     <o.0..1>    P1.0  <0=> GPIO      <1=> SIN       
                       <2=> I2C0SCL <3=> PLAI[0]
  110 00000000         ;//     <o.4..5>    P1.1  <0=> GPIO      <1=> SOUT      
                       <2=> I2C0SDA <3=> PLAI[1]
  111 00000000         ;//     <o.8..9>    P1.2  <0=> GPIO      <1=> RTS       
                       <2=> I2C1SCL <3=> PLAI[2]
  112 00000000         ;//     <o.12..13>  P1.3  <0=> GPIO      <1=> CTS       
                       <2=> I2C1SDA <3=> PLAI[3]
  113 00000000         ;//     <o.16..17>  P1.4  <0=> GPIO/IRQ2 <1=> RI        
                       <2=> SPICLK  <3=> PLAI[4]
  114 00000000         ;//     <o.20..21>  P1.5  <0=> GPIO/IRQ3 <1=> DCD       
                       <2=> SPIMISO <3=> PLAI[5]
  115 00000000         ;//     <o.24..25>  P1.6  <0=> GPIO      <1=> DSR       
                       <2=> SPIMOSI <3=> PLAI[6]
  116 00000000         ;//     <o.28..29>  P1.7  <0=> GPIO      <1=> DTR       
                       <2=> SPICSL  <3=> PLAO[0]
  117 00000000         ;//   </h>
  118 00000000 00000000 
                       GP1CON_Val
                               EQU              0x00000000
  119 00000000         
  120 00000000         ;//   <h>  Port 2
  121 00000000         ;//     <o.0..1>    P2.0  <0=> GPIO      <1=> CONVSTART 
                       <2=> SOUT    <3=> PLAO[5]
  122 00000000         ;//     <o.4..5>    P2.1  <0=> GPIO      <1=> ---       
                       <2=> XWS     <3=> PLAO[6]
  123 00000000         ;//     <o.8..9>    P2.2  <0=> GPIO      <1=> ---       
                       <2=> XRS     <3=> PLAO[7]
  124 00000000         ;//     <o.12..13>  P2.3  <0=> GPIO      <1=> ---       
                       <2=> XAE     <3=> ---
  125 00000000         ;//     <o.16..17>  P2.4  <0=> GPIO      <1=> ---       
                       <2=> MS0     <3=> ---
  126 00000000         ;//     <o.20..21>  P2.5  <0=> GPIO      <1=> ---       
                       <2=> MS1     <3=> ---
  127 00000000         ;//     <o.24..25>  P2.6  <0=> GPIO      <1=> ---       
                       <2=> MS2     <3=> ---
  128 00000000         ;//     <o.28..29>  P2.7  <0=> GPIO      <1=> ---       
                       <2=> MS3     <3=> ---
  129 00000000         ;//   </h>
  130 00000000 00000000 
                       GP2CON_Val
                               EQU              0x00000000
  131 00000000         



ARM Macro Assembler    Page 5 


  132 00000000         ;//   <h>  Port 3
  133 00000000         ;//     <o.0..1>    P3.0  <0=> GPIO      <1=> PWM0H     
                       <2=> XAD0    <3=> PLAI[8]
  134 00000000         ;//     <o.4..5>    P3.1  <0=> GPIO      <1=> PWM0L     
                       <2=> XAD1    <3=> PLAI[9]
  135 00000000         ;//     <o.8..9>    P3.2  <0=> GPIO      <1=> PWM1H     
                       <2=> XAD2    <3=> PLAI[10]
  136 00000000         ;//     <o.12..13>  P3.3  <0=> GPIO      <1=> PWM1L     
                       <2=> XAD3    <3=> PLAI[11]
  137 00000000         ;//     <o.16..17>  P3.4  <0=> GPIO      <1=> PWM2H     
                       <2=> XAD4    <3=> PLAI[12]
  138 00000000         ;//     <o.20..21>  P3.5  <0=> GPIO      <1=> PWM2L     
                       <2=> XAD5    <3=> PLAI[13]
  139 00000000         ;//     <o.24..25>  P3.6  <0=> GPIO      <1=> PWMTRIP   
                       <2=> XAD6    <3=> PLAI[14]
  140 00000000         ;//     <o.28..29>  P3.7  <0=> GPIO      <1=> PWMSYNC   
                       <2=> XAD7    <3=> PLAI[15]
  141 00000000         ;//   </h>
  142 00000000 00000000 
                       GP3CON_Val
                               EQU              0x00000000
  143 00000000         
  144 00000000         ;//   <h>  Port 4
  145 00000000         ;//     <o.0..1>    P4.0  <0=> GPIO      <1=> ---       
                       <2=> XAD8    <3=> PLAO[8]
  146 00000000         ;//     <o.4..5>    P4.1  <0=> GPIO      <1=> ---       
                       <2=> XAD9    <3=> PLAO[9]
  147 00000000         ;//     <o.8..9>    P4.2  <0=> GPIO      <1=> ---       
                       <2=> XAD10   <3=> PLAO[10]
  148 00000000         ;//     <o.12..13>  P4.3  <0=> GPIO      <1=> ---       
                       <2=> XAD11   <3=> PLAO[11]
  149 00000000         ;//     <o.16..17>  P4.4  <0=> GPIO      <1=> ---       
                       <2=> XAD12   <3=> PLAO[12]
  150 00000000         ;//     <o.20..21>  P4.5  <0=> GPIO      <1=> ---       
                       <2=> XAD13   <3=> PLAO[13]
  151 00000000         ;//     <o.24..25>  P4.6  <0=> GPIO      <1=> ---       
                       <2=> XAD14   <3=> PLAO[14]
  152 00000000         ;//     <o.28..29>  P4.7  <0=> GPIO      <1=> ---       
                       <2=> XAD15   <3=> PLAO[15]
  153 00000000         ;//   </h>
  154 00000000 00000000 
                       GP4CON_Val
                               EQU              0x00000000
  155 00000000         
  156 00000000         ;// </e>
  157 00000000         
  158 00000000         
  159 00000000         ;// <e> External Memory Interface
  160 00000000 00000000 
                       XM_SETUP
                               EQU              0
  161 00000000 FFFFF000 
                       XMBASE  EQU              0xFFFFF000
  162 00000000         
  163 00000000         ;//   <e.0>  Enable Memory Region 0
  164 00000000         ;//     <o.1>       Data Bus Width  <0=> 8-bit  <1=> 16-
                       bit
  165 00000000         ;//     <o1.11>     Enable Dynamic Addressing
  166 00000000         ;//     <o1.15>     Byte Enabled Write Strobe



ARM Macro Assembler    Page 6 


  167 00000000         ;//     <o1.10>     Disable extra Address Latch Hold Cyc
                       le
  168 00000000         ;//     <o1.8>      Disable extra Write Address Hold Cyc
                       le
  169 00000000         ;//     <o1.9>      Disable Read Bus Turn Cycle
  170 00000000         ;//     <o1.12..14> Address Wait States <0-7>
  171 00000000         ;//                 <i> Number of Wait States added for 
                       AE
  172 00000000         ;//     <o1.0..3>   Read Wait States <0-15>
  173 00000000         ;//                 <i> Number of Wait States added for 
                       RS
  174 00000000         ;//     <o1.4..7>   Write Wait States <0-15>
  175 00000000         ;//                 <i> Number of Wait States added for 
                       WS
  176 00000000         ;//   </e>
  177 00000000 00000000 
                       XM0CON_Val
                               EQU              0x00000000
  178 00000000 000070FF 
                       XM0PAR_Val
                               EQU              0x000070FF
  179 00000000         
  180 00000000         ;//   <e.0>  Enable Memory Region 1
  181 00000000         ;//     <o.1>       Data Bus Width  <0=> 8-bit  <1=> 16-
                       bit
  182 00000000         ;//     <o1.11>     Enable Dynamic Addressing
  183 00000000         ;//     <o1.15>     Byte Enabled Write Strobe
  184 00000000         ;//     <o1.10>     Disable extra Address Latch Hold Cyc
                       le
  185 00000000         ;//     <o1.8>      Disable extra Write Address Hold Cyc
                       le
  186 00000000         ;//     <o1.9>      Disable Read Bus Turn Cycle
  187 00000000         ;//     <o1.12..14> Address Wait States <0-7>
  188 00000000         ;//                 <i> Number of Wait States added for 
                       AE
  189 00000000         ;//     <o1.0..3>   Read Wait States <0-15>
  190 00000000         ;//                 <i> Number of Wait States added for 
                       RS
  191 00000000         ;//     <o1.4..7>   Write Wait States <0-15>
  192 00000000         ;//                 <i> Number of Wait States added for 
                       WS
  193 00000000         ;//   </e>
  194 00000000 00000000 
                       XM1CON_Val
                               EQU              0x00000000
  195 00000000 000070FF 
                       XM1PAR_Val
                               EQU              0x000070FF
  196 00000000         
  197 00000000         ;//   <e.0>  Enable Memory Region 2
  198 00000000         ;//     <o.1>       Data Bus Width  <0=> 8-bit  <1=> 16-
                       bit
  199 00000000         ;//     <o1.11>     Enable Dynamic Addressing
  200 00000000         ;//     <o1.15>     Byte Enabled Write Strobe
  201 00000000         ;//     <o1.10>     Disable extra Address Latch Hold Cyc
                       le
  202 00000000         ;//     <o1.8>      Disable extra Write Address Hold Cyc
                       le
  203 00000000         ;//     <o1.9>      Disable Read Bus Turn Cycle



ARM Macro Assembler    Page 7 


  204 00000000         ;//     <o1.12..14> Address Wait States <0-7>
  205 00000000         ;//                 <i> Number of Wait States added for 
                       AE
  206 00000000         ;//     <o1.0..3>   Read Wait States <0-15>
  207 00000000         ;//                 <i> Number of Wait States added for 
                       RS
  208 00000000         ;//     <o1.4..7>   Write Wait States <0-15>
  209 00000000         ;//                 <i> Number of Wait States added for 
                       WS
  210 00000000         ;//   </e>
  211 00000000 00000000 
                       XM2CON_Val
                               EQU              0x00000000
  212 00000000 000070FF 
                       XM2PAR_Val
                               EQU              0x000070FF
  213 00000000         
  214 00000000         ;//   <e.0>  Enable Memory Region 3
  215 00000000         ;//     <o.1>       Data Bus Width  <0=> 8-bit  <1=> 16-
                       bit
  216 00000000         ;//     <o1.11>     Enable Dynamic Addressing
  217 00000000         ;//     <o1.15>     Byte Enabled Write Strobe
  218 00000000         ;//     <o1.10>     Disable extra Address Latch Hold Cyc
                       le
  219 00000000         ;//     <o1.8>      Disable extra Write Address Hold Cyc
                       le
  220 00000000         ;//     <o1.9>      Disable Read Bus Turn Cycle
  221 00000000         ;//     <o1.12..14> Address Wait States <0-7>
  222 00000000         ;//                 <i> Number of Wait States added for 
                       AE
  223 00000000         ;//     <o1.0..3>   Read Wait States <0-15>
  224 00000000         ;//                 <i> Number of Wait States added for 
                       RS
  225 00000000         ;//     <o1.4..7>   Write Wait States <0-15>
  226 00000000         ;//                 <i> Number of Wait States added for 
                       WS
  227 00000000         ;//   </e>
  228 00000000 00000000 
                       XM3CON_Val
                               EQU              0x00000000
  229 00000000 000070FF 
                       XM3PAR_Val
                               EQU              0x000070FF
  230 00000000         
  231 00000000         ;//   <e.0>         Memory Muxed Mode
  232 00000000 00000001 
                       XMCFG_Val
                               EQU              0x00000001
  233 00000000         ;//   </e>
  234 00000000         
  235 00000000         ;// </e>
  236 00000000         
  237 00000000         
  238 00000000                 PRESERVE8
  239 00000000         
  240 00000000         
  241 00000000         ; Area Definition and Entry Point
  242 00000000         ;  Startup Code must be linked first at Address at which
                        it expects to run.



ARM Macro Assembler    Page 8 


  243 00000000         
  244 00000000                 AREA             Reset, CODE, READONLY
  245 00000000                 ARM
  246 00000000         
  247 00000000         
  248 00000000         ; Exception Vectors
  249 00000000         ;  Mapped to Address 0.
  250 00000000         ;  Absolute addressing mode must be used.
  251 00000000         ;  Dummy Handlers are implemented as infinite loops whic
                       h can be modified.
  252 00000000         
  253 00000000 E59FF018 
                       Vectors LDR              PC, Reset_Addr
  254 00000004 E59FF018        LDR              PC, Undef_Addr
  255 00000008 E59FF018        LDR              PC, SWI_Addr
  256 0000000C E59FF018        LDR              PC, PAbt_Addr
  257 00000010 E59FF018        LDR              PC, DAbt_Addr
  258 00000014 FFFFFFFF        DCD              0xFFFFFFFF  ; Reserved Vector 
  259 00000018 E59FF018        LDR              PC, IRQ_Addr
  260 0000001C E59FF018        LDR              PC, FIQ_Addr
  261 00000020         
  262 00000020                 EXTERN           Undef_Handler
  263 00000020                 EXTERN           SWI_Handler
  264 00000020                 EXTERN           PAbt_Handler
  265 00000020                 EXTERN           DAbt_Handler
  266 00000020                 EXTERN           IRQ_Handler
  267 00000020                 EXTERN           FIQ_Handler
  268 00000020         
  269 00000020 00000000 
                       Reset_Addr
                               DCD              Reset_Handler
  270 00000024 00000000 
                       Undef_Addr
                               DCD              Undef_Handler
  271 00000028 00000000 
                       SWI_Addr
                               DCD              SWI_Handler
  272 0000002C 00000000 
                       PAbt_Addr
                               DCD              PAbt_Handler
  273 00000030 00000000 
                       DAbt_Addr
                               DCD              DAbt_Handler
  274 00000034 FFFFFFFF        DCD              0xFFFFFFFF  ; Reserved Address 
                                                            
  275 00000038 00000000 
                       IRQ_Addr
                               DCD              IRQ_Handler
  276 0000003C 00000000 
                       FIQ_Addr
                               DCD              FIQ_Handler
  277 00000040         
  278 00000040         
  279 00000040         ; Reset Handler
  280 00000040         
  281 00000040                 EXPORT           Reset_Handler
  282 00000040         Reset_Handler
  283 00000040         
  284 00000040         



ARM Macro Assembler    Page 9 


  285 00000040         ; Setup PLL
  286 00000040                 IF               PLL_SETUP <> 0
  287 00000040 E59F0068        LDR              R0, =MMR_BASE
  288 00000044 E3A01001        MOV              R1, #0x01
  289 00000048 E5801404        STR              R1, [R0,#POWKEY1_OFFSET]
  290 0000004C E3A01001        MOV              R1, #PLLCFG_Val
  291 00000050 E5801408        STR              R1, [R0,#POWCON_OFFSET]
  292 00000054 E3A010F4        MOV              R1, #0xF4
  293 00000058 E580140C        STR              R1, [R0,#POWKEY2_OFFSET]
  294 0000005C                 ENDIF                        ; PLL_SETUP
  295 0000005C         
  296 0000005C         
  297 0000005C         ; Setup Pins
  298 0000005C                 IF               GPIO_SETUP <> 0
  313                          ENDIF                        ; GPIO_SETUP
  314 0000005C         
  315 0000005C         
  316 0000005C         ; Setup External Memory Interface
  317 0000005C                 IF               XM_SETUP <> 0
  337                          ENDIF                        ; XM_SETUP
  338 0000005C         
  339 0000005C         
  340 0000005C         ; Copy Exception Vectors to Internal RAM and Remap Memor
                       y
  341 0000005C         ;  (when Interrupt Vectors are in RAM)
  342 0000005C         
  343 0000005C                 IF               :DEF:RAM_INTVEC
  353                          ENDIF
  354 0000005C         
  355 0000005C         
  356 0000005C         ; Setup Stack for each mode
  357 0000005C         
  358 0000005C E59F0050        LDR              R0, =Stack_Top
  359 00000060         
  360 00000060         ;  Enter Undefined Instruction Mode and set its Stack Po
                       inter
  361 00000060 E321F0DB        MSR              CPSR_c, #Mode_UND:OR:I_Bit:OR:F
_Bit
  362 00000064 E1A0D000        MOV              SP, R0
  363 00000068 E2400080        SUB              R0, R0, #UND_Stack_Size
  364 0000006C         
  365 0000006C         ;  Enter Abort Mode and set its Stack Pointer
  366 0000006C E321F0D7        MSR              CPSR_c, #Mode_ABT:OR:I_Bit:OR:F
_Bit
  367 00000070 E1A0D000        MOV              SP, R0
  368 00000074 E2400080        SUB              R0, R0, #ABT_Stack_Size
  369 00000078         
  370 00000078         ;  Enter FIQ Mode and set its Stack Pointer
  371 00000078 E321F0D1        MSR              CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F
_Bit
  372 0000007C E1A0D000        MOV              SP, R0
  373 00000080 E2400080        SUB              R0, R0, #FIQ_Stack_Size
  374 00000084         
  375 00000084         ;  Enter IRQ Mode and set its Stack Pointer
  376 00000084 E321F0D2        MSR              CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F
_Bit
  377 00000088 E1A0D000        MOV              SP, R0
  378 0000008C E2400080        SUB              R0, R0, #IRQ_Stack_Size
  379 00000090         



ARM Macro Assembler    Page 10 


  380 00000090         ;  Enter Supervisor Mode and set its Stack Pointer
  381 00000090 E321F0D3        MSR              CPSR_c, #Mode_SVC:OR:I_Bit:OR:F
_Bit
  382 00000094 E1A0D000        MOV              SP, R0
  383 00000098 E2400080        SUB              R0, R0, #SVC_Stack_Size
  384 0000009C         
  385 0000009C         ;  Enter User Mode and set its Stack Pointer
  386 0000009C E321F010        MSR              CPSR_c, #Mode_USR
  387 000000A0 E1A0D000        MOV              SP, R0
  388 000000A4 E24DAB01        SUB              SL, SP, #USR_Stack_Size
  389 000000A8         
  390 000000A8         
  391 000000A8         ; Enter the C code
  392 000000A8         
  393 000000A8                 IMPORT           __main
  394 000000A8 E59F0008        LDR              R0, =__main
  395 000000AC E12FFF10        BX               R0
  396 000000B0         
  397 000000B0         
  398 000000B0         ; User Initial Stack & Heap
  399 000000B0 FFFF0000 
              00000000 
              00000000         AREA             |.text|, CODE, READONLY
  400 00000000         
  401 00000000                 IMPORT           __use_two_region_memory
  402 00000000                 EXPORT           __user_initial_stackheap
  403 00000000         __user_initial_stackheap
  404 00000000         
  405 00000000 E59F000C        LDR              R0, =  Heap_Mem
  406 00000004 E59F100C        LDR              R1, =(Stack_Mem + USR_Stack_Siz
e)
  407 00000008 E59F2004        LDR              R2, = (Heap_Mem +      Heap_Siz
e)
  408 0000000C E59F3008        LDR              R3, = Stack_Mem
  409 00000010 E12FFF1E        BX               LR
  410 00000014         
  411 00000014         
  412 00000014                 END
              00000000 
              00000400 
              00000000 
Command Line: --debug --xref --device=DARMAD --apcs=interwork -oADuC702x.o -IC:
\Keil\ARM\INC\ADI --predefine="__EVAL SETA 1" --list=ADuC702x.lst ADuC702x.s



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

STACK 00000000

Symbol: STACK
   Definitions
      At line 57 in file ADuC702x.s
   Uses
      None
Comment: STACK unused
Stack_Mem 00000000

Symbol: Stack_Mem
   Definitions
      At line 58 in file ADuC702x.s
   Uses
      At line 60 in file ADuC702x.s
      At line 406 in file ADuC702x.s
      At line 408 in file ADuC702x.s

Stack_Top 00000680

Symbol: Stack_Top
   Definitions
      At line 60 in file ADuC702x.s
   Uses
      At line 358 in file ADuC702x.s
Comment: Stack_Top used once
3 symbols



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

HEAP 00000000

Symbol: HEAP
   Definitions
      At line 69 in file ADuC702x.s
   Uses
      None
Comment: HEAP unused
Heap_Mem 00000000

Symbol: Heap_Mem
   Definitions
      At line 70 in file ADuC702x.s
   Uses
      At line 405 in file ADuC702x.s
      At line 407 in file ADuC702x.s

2 symbols



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

DAbt_Addr 00000030

Symbol: DAbt_Addr
   Definitions
      At line 273 in file ADuC702x.s
   Uses
      At line 257 in file ADuC702x.s
Comment: DAbt_Addr used once
FIQ_Addr 0000003C

Symbol: FIQ_Addr
   Definitions
      At line 276 in file ADuC702x.s
   Uses
      At line 260 in file ADuC702x.s
Comment: FIQ_Addr used once
IRQ_Addr 00000038

Symbol: IRQ_Addr
   Definitions
      At line 275 in file ADuC702x.s
   Uses
      At line 259 in file ADuC702x.s
Comment: IRQ_Addr used once
PAbt_Addr 0000002C

Symbol: PAbt_Addr
   Definitions
      At line 272 in file ADuC702x.s
   Uses
      At line 256 in file ADuC702x.s
Comment: PAbt_Addr used once
Reset 00000000

Symbol: Reset
   Definitions
      At line 244 in file ADuC702x.s
   Uses
      None
Comment: Reset unused
Reset_Addr 00000020

Symbol: Reset_Addr
   Definitions
      At line 269 in file ADuC702x.s
   Uses
      At line 253 in file ADuC702x.s
Comment: Reset_Addr used once
Reset_Handler 00000040

Symbol: Reset_Handler
   Definitions
      At line 282 in file ADuC702x.s
   Uses
      At line 269 in file ADuC702x.s
      At line 281 in file ADuC702x.s

SWI_Addr 00000028




ARM Macro Assembler    Page 2 Alphabetic symbol ordering
Relocatable symbols

Symbol: SWI_Addr
   Definitions
      At line 271 in file ADuC702x.s
   Uses
      At line 255 in file ADuC702x.s
Comment: SWI_Addr used once
Undef_Addr 00000024

Symbol: Undef_Addr
   Definitions
      At line 270 in file ADuC702x.s
   Uses
      At line 254 in file ADuC702x.s
Comment: Undef_Addr used once
Vectors 00000000

Symbol: Vectors
   Definitions
      At line 253 in file ADuC702x.s
   Uses
      None
Comment: Vectors unused
10 symbols



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

.text 00000000

Symbol: .text
   Definitions
      At line 399 in file ADuC702x.s
   Uses
      None
Comment: .text unused
__user_initial_stackheap 00000000

Symbol: __user_initial_stackheap
   Definitions
      At line 403 in file ADuC702x.s
   Uses
      At line 402 in file ADuC702x.s
Comment: __user_initial_stackheap used once
2 symbols



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Absolute symbols

ABT_Stack_Size 00000080

Symbol: ABT_Stack_Size
   Definitions
      At line 49 in file ADuC702x.s
   Uses
      At line 55 in file ADuC702x.s
      At line 368 in file ADuC702x.s

FIQ_Stack_Size 00000080

Symbol: FIQ_Stack_Size
   Definitions
      At line 50 in file ADuC702x.s
   Uses
      At line 55 in file ADuC702x.s
      At line 373 in file ADuC702x.s

F_Bit 00000040

Symbol: F_Bit
   Definitions
      At line 35 in file ADuC702x.s
   Uses
      At line 361 in file ADuC702x.s
      At line 366 in file ADuC702x.s
      At line 371 in file ADuC702x.s
      At line 376 in file ADuC702x.s
      At line 381 in file ADuC702x.s

GP0CON_Val 00000000

Symbol: GP0CON_Val
   Definitions
      At line 106 in file ADuC702x.s
   Uses
      None
Comment: GP0CON_Val unused
GP1CON_Val 00000000

Symbol: GP1CON_Val
   Definitions
      At line 118 in file ADuC702x.s
   Uses
      None
Comment: GP1CON_Val unused
GP2CON_Val 00000000

Symbol: GP2CON_Val
   Definitions
      At line 130 in file ADuC702x.s
   Uses
      None
Comment: GP2CON_Val unused
GP3CON_Val 00000000

Symbol: GP3CON_Val
   Definitions
      At line 142 in file ADuC702x.s



ARM Macro Assembler    Page 2 Alphabetic symbol ordering
Absolute symbols

   Uses
      None
Comment: GP3CON_Val unused
GP4CON_Val 00000000

Symbol: GP4CON_Val
   Definitions
      At line 154 in file ADuC702x.s
   Uses
      None
Comment: GP4CON_Val unused
GPIOBASE FFFFF400

Symbol: GPIOBASE
   Definitions
      At line 94 in file ADuC702x.s
   Uses
      None
Comment: GPIOBASE unused
GPIO_SETUP 00000000

Symbol: GPIO_SETUP
   Definitions
      At line 93 in file ADuC702x.s
   Uses
      At line 298 in file ADuC702x.s
Comment: GPIO_SETUP used once
Heap_Size 00000000

Symbol: Heap_Size
   Definitions
      At line 67 in file ADuC702x.s
   Uses
      At line 70 in file ADuC702x.s
      At line 407 in file ADuC702x.s

IRQ_Stack_Size 00000080

Symbol: IRQ_Stack_Size
   Definitions
      At line 51 in file ADuC702x.s
   Uses
      At line 55 in file ADuC702x.s
      At line 378 in file ADuC702x.s

I_Bit 00000080

Symbol: I_Bit
   Definitions
      At line 34 in file ADuC702x.s
   Uses
      At line 361 in file ADuC702x.s
      At line 366 in file ADuC702x.s
      At line 371 in file ADuC702x.s
      At line 376 in file ADuC702x.s
      At line 381 in file ADuC702x.s

MMR_BASE FFFF0000




ARM Macro Assembler    Page 3 Alphabetic symbol ordering
Absolute symbols

Symbol: MMR_BASE
   Definitions
      At line 74 in file ADuC702x.s
   Uses
      At line 287 in file ADuC702x.s
Comment: MMR_BASE used once
Mode_ABT 00000017

Symbol: Mode_ABT
   Definitions
      At line 30 in file ADuC702x.s
   Uses
      At line 366 in file ADuC702x.s
Comment: Mode_ABT used once
Mode_FIQ 00000011

Symbol: Mode_FIQ
   Definitions
      At line 27 in file ADuC702x.s
   Uses
      At line 371 in file ADuC702x.s
Comment: Mode_FIQ used once
Mode_IRQ 00000012

Symbol: Mode_IRQ
   Definitions
      At line 28 in file ADuC702x.s
   Uses
      At line 376 in file ADuC702x.s
Comment: Mode_IRQ used once
Mode_SVC 00000013

Symbol: Mode_SVC
   Definitions
      At line 29 in file ADuC702x.s
   Uses
      At line 381 in file ADuC702x.s
Comment: Mode_SVC used once
Mode_SYS 0000001F

Symbol: Mode_SYS
   Definitions
      At line 32 in file ADuC702x.s
   Uses
      None
Comment: Mode_SYS unused
Mode_UND 0000001B

Symbol: Mode_UND
   Definitions
      At line 31 in file ADuC702x.s
   Uses
      At line 361 in file ADuC702x.s
Comment: Mode_UND used once
Mode_USR 00000010

Symbol: Mode_USR
   Definitions
      At line 26 in file ADuC702x.s



ARM Macro Assembler    Page 4 Alphabetic symbol ordering
Absolute symbols

   Uses
      At line 386 in file ADuC702x.s
Comment: Mode_USR used once
PLLCFG_Val 00000001

Symbol: PLLCFG_Val
   Definitions
      At line 89 in file ADuC702x.s
   Uses
      At line 290 in file ADuC702x.s
Comment: PLLCFG_Val used once
PLL_SETUP 00000001

Symbol: PLL_SETUP
   Definitions
      At line 88 in file ADuC702x.s
   Uses
      At line 286 in file ADuC702x.s
Comment: PLL_SETUP used once
POWCON_OFFSET 00000408

Symbol: POWCON_OFFSET
   Definitions
      At line 77 in file ADuC702x.s
   Uses
      At line 291 in file ADuC702x.s
Comment: POWCON_OFFSET used once
POWKEY1_OFFSET 00000404

Symbol: POWKEY1_OFFSET
   Definitions
      At line 76 in file ADuC702x.s
   Uses
      At line 289 in file ADuC702x.s
Comment: POWKEY1_OFFSET used once
POWKEY2_OFFSET 0000040C

Symbol: POWKEY2_OFFSET
   Definitions
      At line 78 in file ADuC702x.s
   Uses
      At line 293 in file ADuC702x.s
Comment: POWKEY2_OFFSET used once
REMAP_OFFSET 00000220

Symbol: REMAP_OFFSET
   Definitions
      At line 75 in file ADuC702x.s
   Uses
      None
Comment: REMAP_OFFSET unused
SVC_Stack_Size 00000080

Symbol: SVC_Stack_Size
   Definitions
      At line 48 in file ADuC702x.s
   Uses
      At line 55 in file ADuC702x.s
      At line 383 in file ADuC702x.s



ARM Macro Assembler    Page 5 Alphabetic symbol ordering
Absolute symbols


Stack_Size 00000680

Symbol: Stack_Size
   Definitions
      At line 55 in file ADuC702x.s
   Uses
      At line 58 in file ADuC702x.s
      At line 60 in file ADuC702x.s

UND_Stack_Size 00000080

Symbol: UND_Stack_Size
   Definitions
      At line 47 in file ADuC702x.s
   Uses
      At line 55 in file ADuC702x.s
      At line 363 in file ADuC702x.s

USR_Stack_Size 00000400

Symbol: USR_Stack_Size
   Definitions
      At line 52 in file ADuC702x.s
   Uses
      At line 55 in file ADuC702x.s
      At line 388 in file ADuC702x.s
      At line 406 in file ADuC702x.s

XM0CON_Val 00000000

Symbol: XM0CON_Val
   Definitions
      At line 177 in file ADuC702x.s
   Uses
      None
Comment: XM0CON_Val unused
XM0PAR_Val 000070FF

Symbol: XM0PAR_Val
   Definitions
      At line 178 in file ADuC702x.s
   Uses
      None
Comment: XM0PAR_Val unused
XM1CON_Val 00000000

Symbol: XM1CON_Val
   Definitions
      At line 194 in file ADuC702x.s
   Uses
      None
Comment: XM1CON_Val unused
XM1PAR_Val 000070FF

Symbol: XM1PAR_Val
   Definitions
      At line 195 in file ADuC702x.s
   Uses



ARM Macro Assembler    Page 6 Alphabetic symbol ordering
Absolute symbols

      None
Comment: XM1PAR_Val unused
XM2CON_Val 00000000

Symbol: XM2CON_Val
   Definitions
      At line 211 in file ADuC702x.s
   Uses
      None
Comment: XM2CON_Val unused
XM2PAR_Val 000070FF

Symbol: XM2PAR_Val
   Definitions
      At line 212 in file ADuC702x.s
   Uses
      None
Comment: XM2PAR_Val unused
XM3CON_Val 00000000

Symbol: XM3CON_Val
   Definitions
      At line 228 in file ADuC702x.s
   Uses
      None
Comment: XM3CON_Val unused
XM3PAR_Val 000070FF

Symbol: XM3PAR_Val
   Definitions
      At line 229 in file ADuC702x.s
   Uses
      None
Comment: XM3PAR_Val unused
XMBASE FFFFF000

Symbol: XMBASE
   Definitions
      At line 161 in file ADuC702x.s
   Uses
      None
Comment: XMBASE unused
XMCFG_Val 00000001

Symbol: XMCFG_Val
   Definitions
      At line 232 in file ADuC702x.s
   Uses
      None
Comment: XMCFG_Val unused
XM_SETUP 00000000

Symbol: XM_SETUP
   Definitions
      At line 160 in file ADuC702x.s
   Uses
      At line 317 in file ADuC702x.s
Comment: XM_SETUP used once
42 symbols



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
External symbols

DAbt_Handler 00000000

Symbol: DAbt_Handler
   Definitions
      At line 265 in file ADuC702x.s
   Uses
      At line 273 in file ADuC702x.s
Comment: DAbt_Handler used once
FIQ_Handler 00000000

Symbol: FIQ_Handler
   Definitions
      At line 267 in file ADuC702x.s
   Uses
      At line 276 in file ADuC702x.s
Comment: FIQ_Handler used once
IRQ_Handler 00000000

Symbol: IRQ_Handler
   Definitions
      At line 266 in file ADuC702x.s
   Uses
      At line 275 in file ADuC702x.s
Comment: IRQ_Handler used once
PAbt_Handler 00000000

Symbol: PAbt_Handler
   Definitions
      At line 264 in file ADuC702x.s
   Uses
      At line 272 in file ADuC702x.s
Comment: PAbt_Handler used once
SWI_Handler 00000000

Symbol: SWI_Handler
   Definitions
      At line 263 in file ADuC702x.s
   Uses
      At line 271 in file ADuC702x.s
Comment: SWI_Handler used once
Undef_Handler 00000000

Symbol: Undef_Handler
   Definitions
      At line 262 in file ADuC702x.s
   Uses
      At line 270 in file ADuC702x.s
Comment: Undef_Handler used once
__main 00000000

Symbol: __main
   Definitions
      At line 393 in file ADuC702x.s
   Uses
      At line 394 in file ADuC702x.s
Comment: __main used once
__use_two_region_memory 00000000

Symbol: __use_two_region_memory



ARM Macro Assembler    Page 2 Alphabetic symbol ordering
External symbols

   Definitions
      At line 401 in file ADuC702x.s
   Uses
      None
Comment: __use_two_region_memory unused
8 symbols
391 symbols in table